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ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 1 of 61 1 - 888 - 824 - 4184 ia80c152 universal communications controller data sheet ? ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 2 of 61 1 - 888 - 824 - 4184 copyright 2010 by innovasic semiconductor, inc. published by innovasic semiconductor, inc. 3737 princeton drive ne, suite 130, albuquerque, nm 87107 intel ? is a registered trademark of intel corporation. miles? is a trademark of innovasic semiconductor, inc. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 3 of 61 1 - 888 - 824 - 4184 table of contents list of figures ................................ ................................ ................................ ................................ .. 5 list of tables ................................ ................................ ................................ ................................ ... 6 1. introduction ................................ ................................ ................................ ............................. 7 1.1 general description ................................ ................................ ................................ ....... 7 1.2 features ................................ ................................ ................................ ......................... 8 2. packaging, pin descriptions, and physical dimensions ................................ ......................... 9 2.1 packages and pinouts ................................ ................................ ................................ .... 9 2.1.1 ja/jc ................................ ................................ ................................ ............... 10 2.1.2 jb/jd ................................ ................................ ................................ ............... 13 2.1.3 physical dimensions ................................ ................................ ....................... 16 2.2 i/o signal d escription ................................ ................................ ................................ . 17 3. maximum ratings, thermal characteristics, and dc parameters ................................ ....... 20 4. device architecture ................................ ................................ ................................ .............. 22 4.1 functional block diagram ................................ ................................ .......................... 22 4.2 memory space ................................ ................................ ................................ ............. 23 5. peripheral architecture ................................ ................................ ................................ ......... 25 5.1 registers and interrupts ................................ ................................ ............................... 25 5.2 register set descriptions ................................ ................................ ............................ 27 5.2 .1 a* (0e0h) ................................ ................................ ................................ ....... 27 5.2.2 adr0,1,2,3 (095h, 0a5h, 0b5h, 0c5h) ................................ .......................... 27 5.2.3 amsk0,1 (0d5h, 0e5h) ................................ ................................ ................. 28 5.2.4 b* (0f0h) ................................ ................................ ................................ ........ 28 5.2.5 baud (094h) ................................ ................................ ................................ . 28 5.2.6 bcrl0, bcrh0 (0e2h, 0e3h) ................................ ................................ ...... 28 5.2.7 bcrl1, bcrh1 (0f2h, 0f3h) ................................ ................................ ....... 28 5.2.8 bkoff (0c4h) ................................ ................................ ............................... 28 5.2.9 darl0, darh0 (0c2h, 0c3h) ................................ ................................ ..... 28 5.2.10 darl1, darh1 (0d2h, 0d3h) ................................ ................................ ..... 29 5.2.11 dcon0,1 (092h, 093h) ................................ ................................ .................. 29 5.2.12 dpl, dph (082h, 083h) ................................ ................................ ................. 30 5.2.13 gmod (084h) ................................ ................................ ................................ 30 5.2.14 ie* (0a8h) ................................ ................................ ................................ ...... 31 5.2.15 ien1* (0c8h) ................................ ................................ ................................ . 32 5.2.16 ifs (0a4h) ................................ ................................ ................................ ...... 32 5.2.17 ip* (0b8h) ................................ ................................ ................................ ...... 33 5.2.18 ipn1* (0f8h) ................................ ................................ ................................ .. 33 5.2.19 myslot (0f5h) ................................ ................................ ............................ 34 5.2.20 p0*, p1*, p2*, p3*, p4*, p5, p6 (080h, 090h, 0a0h, 0boh, 0c0h, 091h, 0a1h) ................................ ................................ ................................ .... 34 5.2.21 pcon (087h) ................................ ................................ ................................ .. 35 5.2.22 prbs (0e4h) ................................ ................................ ................................ .. 36 ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 4 of 61 1 - 888 - 824 - 4184 5.2.23 psw* (0d0h) ................................ ................................ ................................ .. 36 5.2.24 rfifo (0f4h) ................................ ................................ ................................ . 37 5.2.25 rstat* (0e8h) ................................ ................................ .............................. 37 5.2.26 sarl0, sarh0 (0a2h, 0a3h) ................................ ................................ ...... 38 5.2.27 sarl1, sarh1 (0b2h, 0b3h) ................................ ................................ ...... 38 5.2.28 sbuf (099h) ................................ ................................ ................................ ... 38 5.2.29 scon* (098h) ................................ ................................ ................................ 38 5.2.30 slottm (0b4h) ................................ ................................ ............................ 39 5.2.31 sp (081h) ................................ ................................ ................................ ........ 39 5.2.32 tcdcnt (0d4h) ................................ ................................ ............................ 39 5.2.33 tcon* (088h) ................................ ................................ ................................ 39 5.2.34 tfifo (085h) ................................ ................................ ................................ .. 40 5.2.35 th0, tl0 (08ch, 08ah) ................................ ................................ ................. 40 5.2.36 th1, tl1 (08dh, 08bh) ................................ ................................ ................. 41 5.2.37 tmod (089h) ................................ ................................ ................................ . 4 1 5.2.38 tstat* (0d8h) ................................ ................................ ............................. 41 5.3 power conservation modes ................................ ................................ ........................ 42 5.4 o scillator pins ................................ ................................ ................................ ............. 43 6. instruction set summary table ................................ ................................ ............................ 50 7. ac characteristics ................................ ................................ ................................ ................ 56 8. innovasic/intel part number cross - reference table ................................ ........................... 57 9. errata ................................ ................................ ................................ ................................ ..... 58 9.1 errata summary ................................ ................................ ................................ ........... 58 9.2 errata detail ................................ ................................ ................................ ................ 58 10. revision history ................................ ................................ ................................ ................... 60 11. for additional information ................................ ................................ ................................ ... 61 ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 5 of 61 1 - 888 - 824 - 4184 list of figures figure 1. ja/jc versions package diagram ................................ ................................ ................. 10 figure 2. jb/jd versions package diagram ................................ ................................ ................. 13 figure 3 . package dimensions ................................ ................................ ................................ ...... 16 figure 4. functional block diagram ................................ ................................ ............................ 22 figure 5. memory space ................................ ................................ ................................ ............... 24 figure 6. external program memory read cycle ................................ ................................ ........ 44 figure 7. external data memory read cycle ................................ ................................ ............... 44 figure 8. external data memory write cycle ................................ ................................ .............. 45 figure 9. external clock drive waveform ................................ ................................ ................... 46 figure 10. shift register mode timing waveforms ................................ ................................ .... 47 figure 11. gsc receiver timings (internal baud rate generator) ................................ ............. 48 figure 12. gsc transmit timings (internal baud rate generator) ................................ ............. 48 figure 13. gsc timings (external clock) ................................ ................................ ................... 49 ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 6 of 61 1 - 888 - 824 - 4184 list of tables table 1. ic version differences ................................ ................................ ................................ ..... 7 table 2 . ja/jc versions numeric pin listing ................................ ................................ .............. 11 table 3 . ja/jc versions alphabetic pin listing ................................ ................................ .......... 12 table 4 . jb/jd versions numeric pin listing ................................ ................................ .............. 14 table 5 . jb/jd versions alphabetic pin listing ................................ ................................ .......... 15 table 6. i/o signal descriptions ................................ ................................ ................................ ... 17 table 7. absolute maximum ratings ................................ ................................ ........................... 20 table 8. thermal characteristics ................................ ................................ ................................ .. 20 table 9. dc parameters ................................ ................................ ................................ ................ 21 table 10. summary of program memory fetches ................................ ................................ ........ 25 table 11. list of registers ................................ ................................ ................................ ............ 25 table 12. list of interrupts ................................ ................................ ................................ ........... 27 table 13. dcon0,1 register ................................ ................................ ................................ ........ 29 table 14. gmod r egister ................................ ................................ ................................ ............ 30 table 15. ie* register ................................ ................................ ................................ .................. 31 table 16. ien1* register ................................ ................................ ................................ ............. 32 table 17. ip* register ................................ ................................ ................................ ................... 33 table 18. ipn1* register ................................ ................................ ................................ .............. 33 table 19. myslot register ................................ ................................ ................................ ........ 34 table 20. p0*, p1*, p2*, p3*, p4*, p5, p6 register ................................ ................................ ..... 35 table 21. pcon register ................................ ................................ ................................ ............. 35 table 22. psw* regi ster ................................ ................................ ................................ .............. 36 table 23. rstat* register ................................ ................................ ................................ ......... 37 table 24. scon* register ................................ ................................ ................................ ........... 38 table 25. tcon* register ................................ ................................ ................................ ........... 40 table 26. tmod register ................................ ................................ ................................ ............ 41 table 27. tmod register ................................ ................................ ................................ ............ 41 table 28. power conservation modes ................................ ................................ .......................... 43 table 29. external clock drive ................................ ................................ ................................ .... 46 table 30. local serial channe l timing shift register mode ................................ ................... 46 table 31. global serial port timing internal baud rate generator ................................ .......... 47 table 32. global serial po rt timing external clock ................................ ................................ . 49 table 33. instruction set summary ................................ ................................ .............................. 50 table 34. external program and data memory characteristics ................................ ................... 56 table 35. innovasic/intel part number cross - reference ................................ ............................. 57 table 36. summary of errata ................................ ................................ ................................ ........ 58 table 37. revision history ................................ ................................ ................................ ........... 60 ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 7 of 61 1 - 888 - 824 - 4184 1. introduction the ia80c152 is a Dplug - and - play drop - in replacement for the original intel 80c152 . innovasic produces replacement ics using its miles, or managed ic lifetime extension system, cloning technology. this technology produces replacement ics far more complex than Demulation while ensuring they are compatible with the original ic. miles captures the design of a clone so it can be produced even as silicon technology advances. miles also verifies the clone against the original ic so that even the Dundocumented features are duplicated. this data sheet presents engineering information about the ia80c152 including functional and i/o descriptions, electrical characteristics, and applicable timing. 1.1 general description the ia80c152 is a universal communications controller (ucc) that is pin - for - pin compatible with the intel 80c152. this version of the ucc is a rom - less version. the rom version is identified as the 83c152 and can be easily derived from the 80c152 using a customer furnished rom program. the ia80c152 can be programmed with the same software development tools and can transmit and receive using the same communication protocols as the intel 80c152 m aking the ia80c152 a drop - in replacement. table 1 below cross - references ia80c152 versions with protocol, package, and i/o port capability. pinout diagrams are provided in figures 1, 2, and 3. table 1 . ic version differences in novasi c part number csma/cd, sdlc/hdlc, user - defined 5 i/o ports 7 i/o ports 68 - lead p lcc ia80c152ja ? ? ? ia80c152jb ? ? ? ia80c152jc ? ? ? ia80c152jd ? ? ? the only difference between the innovasic ia 80c152 and the intel 80c152 is that all pr otocols are available in all ic versions. originally, the intel 80c152 jc and jd versions were limited to sdlc/hdlc only. also, innovasic will support a rom version (83152) in any of the ja, jb, jc, or jd versions. note: if you are using the ia80c1 52jb/jd in a system that originally used an intel 80c152ja/jc, please note that the eben pin on the innovasic part has an internal pull down, so it is recommended that you do not connect that pin (nc) on your board for proper functionality. in addition, t he two ports that are unused on the ja/jc device ( p orts 5 and 6) have internal pullups on the innovasic device, so it is recommended that you do not connect (nc) these pins . ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 8 of 61 1 - 888 - 824 - 4184 the ia80c152 is partitioned into th ree major functional units identified as the c8051, the direct memory access (dma) controller, and the global serial channel (gsc). the c8051 is implemented using a cast, inc. intellectual property (ip) core. this core is instruction set compatible with the 80c51bh, and contains compatible peripherals including a uart interface and timers. the special function registers (sfrs) and interrupts are modified from the original 8051bh to accommodate the additional dma controller and gsc peripherals. the dma co ntroller is a 2 channel, 8 - bit device that is 16 - bit addressable. either channel can access any combination of reads and writes to external memory, internal memory, or the sfr's. various modes allow the dma to access the uart, gsc, sfrs, and internal and external memory as well as provide for external control. since there is only 1 data/program memory bus, only one dma channel or the microcontroller can have control at any give n time. arbitration within the device makes this control transparent to the p rogrammer. the gsc is a serial interface that can be programmed to support csma/cd, sdlc, user definable protocols, and limited hdlc. protocol specific features are supported in hardware such as address recognition, collision resolution, crc generation an d errors, automatic re - transmission, and hardware acknowledge. the csma/cd protocol meets the requirements of iso/iec 8802 - 3 and ansi/ieee std 802.3 to the extent implemented in the original ic. the sdlc protocol meets the requirements of ibm ga27 - 3093 - 0 4 to the extent implemented in the original ic. 1.2 features form, fit, and function compatible with the intel 80c152 packaging options available in both standard and rohs - compliant: C 68 - pin plcc (plastic leaded chip carrier) 8051 core with: C direct memory acce ss (dma) C global serial channel (gsc) C mcs 51 - compatible uart C two timers/counters C maskable interrupts memory : C 256 bytes internal ram C 64k bytes program memory C 64k bytes data memory 5 or 7 i/o ports up to 16.5 - mhz clock frequency two - channel dma with multiple transfer modes gsc provides support for multiple protocols : ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 9 of 61 1 - 888 - 824 - 4184 C csma/cd C sdlc/hdlc C user definable separate transmit & receive fifos special protocol features : C up to 2.0625 mbps serial operation C csma and sdlc frame formats with crc checking C manchester, nrz, & n rzi data encoding C collision detection & resolution in csma mode selectable full/half duplex 2. packaging , pin descriptions, and physical dimensions information on the packages and pin descriptions is provided in this chapter. 2.1 packages and pinouts the ia80c1 52 is available in the following packages: 68 - pin p lcc pinout ja/jc versions 68 - pin p lcc pinout jb/jd versions ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 10 of 61 1 - 888 - 824 - 4184 2.1.1 ja/jc the pinout for the ja/jc package is as shown in figure 1. the corresponding numeric and alphabetic pin listings are provided in tables 2 and 3. figure 1 . ja/jc versions package diagram ? 1 5 1 0 1 1 1 2 1 3 1 4 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 3 2 2 7 2 8 2 9 3 0 3 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 9 8 7 6 5 4 3 2 1 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 p 4 . 5 p 4 . 6 p 4 . 7 n . c . e a n a l e p s e n n n . c . n . c . n . c . n . c . n . c . p 2 . 7 ( a 1 5 ) p 2 . 6 ( a 1 4 ) p 2 . 5 ( a 1 3 ) p 2 . 4 ( a 1 2 ) p 2 . 3 ( a 1 1 ) ( a / d 0 ) p 0 . 0 ( a / d 1 ) p 0 . 1 ( a / d 2 ) p 0 . 2 ( a / d 3 ) p 0 . 3 x t a l 2 x t a l 1 v s s ( a / d 4 ) p 0 . 4 ( a / d 5 ) p 0 . 5 ( a / d 6 ) p 0 . 6 ( a / d 7 ) p 0 . 7 n . c . n . c . n . c . ( a 8 ) p 2 . 0 ( a 9 ) p 2 . 1 ( a 1 0 ) p 2 . 2 p 1 . 5 ( h l d n ) p 1 . 4 ( r x c n ) p 1 . 3 ( t x c n ) p 1 . 2 ( d e n n ) p 1 . 1 ( g t x d ) p 1 . 0 ( g r x d ) v s s v d d n . c . n . c . n . c . n . c . p 4 . 0 p 4 . 1 p 4 . 2 p 4 . 3 p 4 . 4 ( h l d a n ) p 1 . 6 p 1 . 7 n . c . r e s e t n ( r x d ) p 3 . 0 ( t x d ) p 3 . 1 ( i n t 0 n ) p 3 . 2 n . c . ( i n t 1 n ) p 3 . 3 ( t 0 ) p 3 . 4 n . c . n . c . n . c . ( t 1 ) p 3 . 5 ( w r n ) p 3 . 6 ( r d n ) p 3 . 7 n . c . i a 8 0 c 1 5 2 6 8 - p i n l c c j a / j c ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 11 of 61 1 - 888 - 824 - 4184 table 2 . ja/jc versions numeric pin listing pin name pin name 1 n.c. 35 (a/d5) p0.5 2 vdd 36 (a/d6) p0.6 3 vss 37 (a/d7) p0.7 4 p1.0 (grxd) 38 n.c. 5 p1.1 (gtxd) 39 n.c. 6 p1.2 (denn) 40 n.c. 7 p1.3 (txcn) 41 (a8) p2.0 8 p1.4 (rxcn) 42 (a9) p2.1 9 p1.5 (hldn) 43 (a10) p2.2 10 (hldan) p1.6 44 p2.3 (all) 11 p1.7 45 p2.4 (a12) 12 n.c. 46 p2.5 (a13) 13 resetn 47 p2.6 (a14) 14 (rxd) p3.0 48 p2.7 (a15) 15 (txd) p3.1 49 nc 16 (int0n) p3.2 50 nc 17 n.c. 51 n.c. 18 (int1n) p3.3 52 n.c. 19 (t0) p3.4 53 n.c. 20 n.c. 54 psenn 21 n.c. 55 ale 22 n.c. 56 ean 23 (t1) p3.5 57 nc 24 (wrn) p3.6 58 p4.7 25 (rdn) p3.7 59 p4.6 26 n.c. 60 p4.5 27 (a/d0) p0.0 61 p4.4 28 (a/d1) p0.1 62 p4.3 29 (a/d2) p0.2 63 p4.2 30 (a/d3) p0.3 64 p4.1 31 xtal2 65 p4.0 32 xtal1 66 nc 33 vss 67 nc 34 (a/d4) p0.4 68 nc ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 12 of 61 1 - 888 - 824 - 4184 table 3 . ja/jc versions alphabetic pin listing pin name pin name 27 (a/d0) p0.0 40 n.c. 28 (a/d1) p0.1 49 n.c. 29 (a/d2) p0.2 50 n.c. 30 (a/d3) p0.3 51 n.c. 34 (a/d4) p0.4 52 n.c. 35 (a/d5) p0.5 53 n.c. 36 (a/d6) p0.6 57 n.c. 37 (a/d7) p0.7 66 n.c. 41 (a8) p2.0 67 n.c. 4 2 (a9) p2.1 68 n.c. 43 (a10) p2.2 11 p1.7 44 (a11) p2.3 65 p4.0 45 (a12) p2.4 64 p4.1 46 (a13) p2.5 63 p4.2 47 (a14) p2.6 62 p4.3 48 (a15) p2.7 61 p4.4 55 ale 60 p4.5 6 (denn) p1.2 59 p4.6 56 ean 58 p4.7 4 (grxd) p1.0 54 psenn 5 (gtxd) p1.1 25 (rdn) p3.7 10 (hldan) p1.6 13 resetn 9 (hldn) p1.5 8 (rxcn) p1.4 16 (int0n) p3.2 14 (rxd) p3.0 18 (int1n) p3.3 19 (t0) p3.4 1 n.c. 23 (t1) p3.5 12 n.c. 7 (txcn) p1.3 17 n.c. 15 (txd) p3.1 20 n.c. 2 vdd 21 n.c. 3 vss 22 n.c. 33 vss 26 n.c. 24 (wrn) p3.6 38 n.c. 32 xtal1 39 n.c. 31 xtal2 ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 13 of 61 1 - 888 - 824 - 4184 2.1.2 jb/jd the pinout for the jb/jd package is as shown in figure 2. the corresponding pin listings are provided in tables 4 and 5. figure 2 . jb/jd ver sions package diagram ? i a 8 0 c 1 5 2 6 8 - p i n l c c j b / j d 1 5 ( t x d ) p 3 . 1 1 0 ( h l d a n ) p 1 . 6 1 1 p 1 . 7 1 2 e b e n 1 3 r e s e t n 1 4 ( r x d ) p 3 . 0 1 6 ( i n t 0 n ) p 3 . 2 1 7 p 5 . 0 1 8 ( i n t 1 n ) p 3 . 3 1 9 ( t 0 ) p 3 . 4 2 0 p 5 . 1 2 1 p 5 . 2 2 2 p 5 . 3 2 3 ( t 1 ) p 3 . 5 2 4 ( w r n ) p 3 . 6 2 5 ( r d n ) p 3 . 7 2 6 n . c . 6 0 p 4 . 5 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 p 6 . 2 5 1 p 6 . 7 5 0 p 6 . 4 4 9 p 5 . 7 4 8 p 2 . 7 ( a 1 5 ) 4 7 p 2 . 6 ( a 1 4 ) 4 6 4 5 4 4 p 2 . 5 ( a 1 3 ) p 2 . 4 ( a 1 2 ) p 2 . 3 ( a 1 1 ) e p s e n n p s e n n a l e p 6 . 3 p 4 . 7 p 4 . 6 3 2 x t a l 1 2 7 ( a / d 0 ) p 0 . 0 2 8 ( a / d 1 ) p 0 . 1 2 9 ( a / d 2 ) p 0 . 2 3 0 ( a / d 3 ) p 0 . 3 3 1 x t a l 2 3 3 v s s 3 4 ( a / d 4 ) p 0 . 4 3 5 ( a / d 5 ) p 0 . 5 3 6 ( a / d 6 ) p 0 . 6 3 7 ( a / d 7 ) p 0 . 7 3 8 p 5 . 4 3 9 p 5 . 5 4 0 p 5 . 6 4 1 ( a 8 ) p 2 . 0 4 2 ( a 9 ) p 2 . 1 4 3 ( a 1 0 ) p 2 . 2 9 p 1 . 5 ( h l d n ) 8 7 6 5 4 3 2 1 n . c . 6 8 n . c . 6 7 n . c . 6 6 n . c . 6 5 p 4 . 0 6 4 p 4 . 1 6 3 6 2 6 1 p 4 . 2 p 4 . 3 p 4 . 4 v d d v s s p 1 . 0 ( g r x d ) p 1 . 1 ( g t x d ) p 1 . 2 ( d e n n ) p 1 . 3 ( t x c n ) p 1 . 4 ( r x c n ) e a n ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 14 of 61 1 - 888 - 824 - 4184 table 4 . j b /j d versions numeric pin listing pin name pin name 1 n.c. 35 (a/d5) p0.5 2 vdd 36 (a/d6) p0.6 3 vss 37 (a/d7) p0.7 4 p1.0 (grxd) 38 p5.4 5 p1.1 (gtxd) 39 p5.5 6 p1.2 (denn) 40 p5.6 7 p1.3 (txcn) 41 (a8) p2.0 8 p1.4 (rxcn) 42 (a9) p2.1 9 p1.5 (hldn) 43 (a10) p2.2 10 (hldan) p1.6 44 p2.3 (a11) 11 p1.7 45 p2.4 (a12) 12 eben 46 p2.5 (a13) 13 resetn 47 p2.6 (a14) 14 (rxd) p3.0 48 p2.7 (a15) 15 (txd) p3.1 49 p5.7 16 (int0n ) p3.2 50 p6.4 17 p5.0 51 p6.7 18 (int1n) p3.3 52 p6.2 19 (t0) p3.4 53 epsenn 20 p5.1 54 psenn 21 p5.2 55 ale 22 p5.3 56 ean 23 (t1) p3.5 57 p6.3 24 (wrn) p3.6 58 p4.7 25 (rdn) p3.7 59 p4.6 26 n.c. 60 p4.5 27 (a/d0) p0.0 61 p4.4 28 (a/d1) p0.1 62 p4.3 29 (a/d2) p0.2 63 p4.2 30 (a/d3) p0.3 64 p4.1 31 xtal2 65 p4.0 32 xtal1 66 n.c. 33 vss 67 n.c. 34 (a/d4) p0.4 68 n.c. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 15 of 61 1 - 888 - 824 - 4184 table 5 . jb/jd versions alphabetic pin listing pin name pin name 27 (a/d0) p0.0 64 p4.1 28 (a/d1) p0.1 63 p4.2 29 (a/d2) p0.2 62 p4.3 30 (a/d3) p0.3 61 p4.4 34 (a/d4) p0.4 60 p4.5 35 (a/d5) p0.5 59 p4.6 36 (a/d6) p0.6 58 p4.7 37 (a/d7) p0.7 17 p5.0 41 (a8) p2.0 20 p5.1 42 (a9) p2.1 21 p5.2 43 (a10) p2.2 22 p 5.3 44 (a11) p2.3 38 p5.4 45 (a12) p2.4 39 p5.5 46 (a13) p2.5 40 p5.6 47 (a14) p2.6 49 p5.7 48 (a15) p2.7 52 p6.2 55 ale 57 p6.3 6 (denn) p1.2 50 p6.4 56 ean 51 p6.7 12 eben 54 psenn 53 epsenn 25 (rdn) p3.7 4 (grxd) p1.0 13 res etn 5 (gtxd) p1.1 8 (rxcn) p1.4 10 (hldan) p1.6 14 (rxd) p3.0 9 (hldn) p1.5 19 (t0) p3.4 16 (int0n) p3.2 23 (t1) p3.5 18 (int1n) p3.3 7 (txcn) p1.3 1 n.c. 15 (txd) p3.1 26 n.c. 2 vdd 66 n.c. 3 vss 67 n.c. 33 vss 68 n.c. 24 (wrn) p3.6 11 p1.7 32 xtal1 65 p4.0 31 xtal2 ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 16 of 61 1 - 888 - 824 - 4184 2.1.3 physical dimensions the package dimensions are as shown in figure 3. figure 3 . package dimensions legend: symbol 68 (in millimeters) min max a 4.20 5.08 a1 2.29 3.30 d1 24.13 24.33 d2 22.61 23.62 d3 20.32 bsc e1 24.13 24.33 e2 22.61 23.62 e3 20.32 bsc e 1.27 bsc d 25.02 25.27 e 25.02 25.27 ? .10 .51 min. r 1.14 / .64 seating plane a1 e .81 / .66 a .53 / .33 d2 / e2 side view d3 e3 pin 1 identifier & zone 1.22/1.07 2 plcs top view d d1 e e1 bottom view
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 17 of 61 1 - 888 - 824 - 4184 2.2 i/o signal description table 6 below describes the i/o characteristics for each signal on the ic. the signal names corr espond to the signal names on the pinout diagrams provided above. the (n) denotes active low . table 6 . i/o signal descriptions signal name description ean external access enable. since there is no internal rom in the ia 80c152, this signal has no function in the ja and jc versions and should be set to 0. for the jb and jd versions with eben, it controls program memory fetches from ports 0, 2 or ports 5, 6. see table 3. epsenn e - bus program store enable. when eben is 1, this s ignal is the read strobe for external program memory. jb/jd versions only. psenn program store enable. when eben is 0, this signal is the read strobe for external program memory. resetn reset. when this signal is low for 3 machine cycles, the device i s put into reset. the gsc may continue transmitting after reset is applied. an internal pull - up allows the use of an external capacitor to generate a power - on reset. ale address latch enable. latches the low - byte of external memory. eben e - bus enable. in conjunction with ean, eben designates program memory fetches from either port 0,2 or port 5,6. see table 3. p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 port 0 - open drain 8 - bit bi - directional port that is bit addressable and can drive up to 8 ls ttl in puts. the port signals can be used as high impedance inputs. this port also provides the low - byte of the multiplexed address and data bus depending on the state of eben. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 18 of 61 1 - 888 - 824 - 4184 table 6 . i/o signal descriptions (continued) signal name description p1.0 - grxd , gsc receive p1.1 - gtxd, gsc transmit p1.2 - denn, driver enable p1.3 - txcn, external transmit clock p1.4 - rxcn, external receive clock p1.5 - hldn, dma hold p1.6 - hldan, dma hold acknowledge p1.7 port 1 8 - bit bi - directional port that is bit addressab le. to use a port signal as an input, write a 1 to the port location. internal pull - ups pull the input high and source current when the input is driven low. to use a port signal as an output, a 1 or 0 written to the port location is presented at the out put. port signals in this port also serve as i/o for ia 80c152 functions. these i/o signals are defined next to the port name. p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 port 2 8 - bit bi - directional port that is bit addressable. to use a port signal as an i nput, write a 1 to the port location. internal pull - ups pull the input high and source current when the input is driven low. to use a port signal as an output, a 1 or 0 written to the port location is presented at the output. this port also provides the high - byte of the multiplexed address and data bus depending on the state of eben. p3.0 - rxd, uart receive p3.1 - txd, uart transmit p3.2 - int0n, external interrupt 0 p3.3 - int1n, external interrupt 1 p3.4 - t0, timer 0 external input p3.5 - t1, timer 1 external input p3.6 - wrn, external data memory write strobe p3.7 - rdn, external data memory read strobe port 3 8 - bit bi - directional port that is bit addressable. to use a port signal as an input, write a 1 to the port location. internal pull - ups pull the input high and source current when the input is driven low. to use a port signal as an output, a 1 or 0 written to the port location is presented at the output. port signals in this port also serve as i/o for ia 80c152 functions. these i/o signals a re defined next to the port name. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 19 of 61 1 - 888 - 824 - 4184 table 6 . i/o signal descriptions (continued) signal name description p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 port 4 8 - bit bi - directional port that is bit addressable. to use a port signal as an input, write a 1 to the port location. internal pull - ups pull the input high and source current when the input is driven low. to use a port signal as an output, a 1 or 0 written to the port location is presented at the output. p5.0 p5.1 p5.2 p5.3 p5.4 p5.5 p5.6 p5.7 port 5 8 - bit bi - directional port that is not bit addressable. to use the port as an input, write a 1 to the port location. internal pull - ups pull the input high and source current when the input is driven low. to use the port as an output, 1s or 0s written to th e port are presented at the output. this port also provides the low - byte of the multiplexed address and data bus depending on the state of eben. p6.0 p6.1 p6.2 p6.3 p6.4 p6.5 p6.6 p6.7 port 6 8 - bit bi - directional port that is not bit addressable. to use the port as an input, write a 1 to the port location. internal pull - ups pull the input high and source current when the input is driven low. to use the port as an output, 1s or 0s written to the port are presented at the output. this port also provides the high - byte of the multiplexed address and data bus depending on the state of eben. vcc supply voltage vss device ground xtal1 input to the internal clock generator xtal2 output from the internal oscillator amplifier ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 20 of 61 1 - 888 - 824 - 4184 3. maximum ratings, thermal chara cteristics, and dc parameters the absolute maximum ratings, thermal characteristics, and dc parameters are provided in tables 7 through 9 , respectively. the input and output parametric values in the dc and ac characteristics are directly related to ambien t temperature and dc supply voltage. a temperature or supply voltage range other than those specified in the operating conditions may affect these values as well as adversely affect part performance and reliability . stresses beyond those listed in table 7 , absolute maximum ratings, may cause permanent damage to the device. operating the device at or beyond the conditions indicated is not recommended. table 7 . absolute maximum ratings parameter rating storage temperature ?40c to +125c voltage on any pin to v ss ?0.3v to +(v dd + 0.3) v operating temperature - 40c to +85c power dissipation 391.1 mw (95c, 16mhz, 15% toggle) table 8 . thermal characteristics symbol characteristic value t a ambi ent temperature - 40 c to 85 c ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 21 of 61 1 - 888 - 824 - 4184 table 9 . dc parameters symbol parameter min typ max unit test conditions v cc supply voltage 4.5 C 5.5 v C v il input low voltage (all except xtal1) C C 0.9 v C v ih input high voltage (all except xtal1) 2.1 C C v C v ol output low voltage C C 0.4 v C v oh output high voltage (all except port 0 in port mode) 3.5 C C v C C C C C v oh1 output high voltage (port 0 in external bus mode) 3.5 C C v C C C C C C i il logical 0 input current - 1 C 1 a no pullup or pulldown i ih logical 1 input current - 1 C 1 a no pullup or pulldown i oz input leakage ( port 0,1,2,3,4,5,6, ale,psen, epsen) - 10 C 10 a tri - state leakage current rup, rdn pull - up resistor, pull - down resistor C 50 C kw C i dd a power sup ply current: active (16.5 mhz) idle (16.5 mhz) power down mode C C 50 ma C C C ma C C C a C a static idd current is exclusive of input/output drive requirements and is measured with the clocks stopped and all inputs tied to vdd or vss conf igured to draw minimum current. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 22 of 61 1 - 888 - 824 - 4184 4. device architecture 4.1 functional block diagram figure 4 shows the major functional blocks of the ia80c152. each version of the ia80c152 function identically to each other with the exception of the 2 additional i/o ports (p ort 5 and port 6) in the jb and jd versions. figure 4 . functional block diagram ? p o r t 3 p o r t 2 p o r t 1 p o r t 0 2 5 6 x 8 r a m c o n t r o l x t a l r e s e t i / o f o r m e m o r y , g s c , d m a , u a r t , i n t e r r u p t s , a n d t i m e r s c l o c k g e n . & t i m i n g c 8 0 5 1 c p u u a r t a d d r e s s / d a t a m e m o r y c o n t r o l p o r t 4 p o r t 5 p o r t 6 i n t e r r u p t s t i m e r s d m a g s c = j b a n d j d v e r s i o n s o n l y .
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 23 of 61 1 - 888 - 824 - 4184 4.2 memory space memory space is divided up into program and data memory. program memory is all external to the ia80c152. data memory is divided up into external and internal data memory. there can be up to 64k bytes of external program and data memory. internal data memory is 256 bytes that is mapped between ram, sfrs, and register banks. figure 5 diagrams the organization of the ia80c152 memory space. see the c8051 section for further details. program memory is accessed using control signals and ports. on the ja and jc versions of the ia80c152 this access is performed through ports p0 and p2. further, because there is no internal rom, the enti re program memory space is accessed via ports p0 and p2. on the jb and jd version of the ia80c152, program memory access can be through either ports p0 and p2, or ports p5 and p6. which set of ports program memory fetches are made through is controlled b y the input signals ean and eben. table 10 summarizes the ia80c152 versions and the relationship to program memory fetches. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 24 of 61 1 - 888 - 824 - 4184 figure 5 . memory space ? u p p e r 1 2 8 b y t e s e x t e r n a l r a m s f r s p a c e l o w e r 1 2 8 b y t e s i n t e r n a l r a m f f f f h c 0 0 0 h 8 0 0 0 h 4 0 0 0 h 0 0 0 0 h f f h 8 0 h 7 f h 0 0 h
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 25 of 61 1 - 888 - 824 - 4184 table 10 . summary of program memory fetches version fetch control fetch ports fetch signal memory space eben ean psenn epsenn ja, jc n a 0 or 1 p0, p2 active C 0h C ffffh jb, jd 0 0 p0, p2 active C 0h C ffffh 1 0 p5, p6 C active 0h C ffffh 1 1 p5, p6 C active 0h C 1fffh p0, p2 active C 2000h C ffffh 5. p eripheral architecture 5.1 registers and interrupts the ia80c152 combines the register set of the 8051bh and additional sfrs for the dma and gsc functions. likewise, the ia80c152 combines the interrupts of the 8051bh and the interrupts require d by the dma and gsc. tables 11 and 12 list the ia80c152 registers interrupts, respectively. table 11 . list of registers item register name register address functional block description initial value 1 a 0e0h c8051 accumulator 00h 2 adr0 095h gsc address match 0 00h 3 adr1 0a5h gsc address match 1 00h 4 adr2 0b5h gsc address match 2 00h 5 adr3 0c5h gsc address match 3 00h 6 amsk0 0d5h gsc address mask 0 00h 7 amsk1 0e5h gsc address mask 1 00h 8 b 0f0h c8051 b register 00h 9 baud 094h gsc baud rate 00h 10 bcrl0 0e2h dma byte count register (low) 0 x 11 bcrh0 0e3h dma byte count register (high) 0 x 12 bcrl1 0f2h dma byte count register (low) 1 x 13 bcrh1 0f3h dma byte count register (high) 1 x 14 bkoff 0c4h gsc backoff timer x 15 darl 0 0c2h dma destination address register (low) 0 x 16 darh0 0c3h dma destination address register (high) 0 x 17 darl1 0d2h dma destination address register (low) 1 x 18 darh1 0d3h dma destination address register (high) 1 x 19 dcon0 092h dma dma control 0 00h 20 dcon1 093h dma dma control 1 00h 21 dph 083h c8051 data pointer high 00h 22 dpl 082h c8051 data pointer low 00h 23 gmod 084h gsc gsc mode x0000000b 24 ie 0a8h c8051 interrupt enable 0xx00000b 25 ien1 0c8h dma, gsc interrupt enable 1 xx00000 0b ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 26 of 61 1 - 888 - 824 - 4184 table 11 . list of registers (continued) item register name register address functional block description initial value 26 ifs 0a4h gsc interframe space 00h 27 ip 0b8h c8051 interrupt priority xxx00000b 28 ipn1 0f8h dma, gsc interrupt priority 1 xx 000000b 29 myslot 0f5h gsc gsc slot address 00h 30 p0 080h c8051 port 0 0ffh 31 p1 090h c8051 port 1 0ffh 32 p2 0a0h c8051 port 2 0ffh 33 p3 0b0h c8051 port 3 0ffh 34 p4 0c0h c8051 port 4 0ffh 35 p5 091h c8051 port 5 0ffh 36 p6 0a1h c8051 port 6 0f fh 37 pcon 087h c8051 power control 0xxx0000b 38 prbs 0e4h gsc pseudo - random sequence 00h 39 psw 0d0h c8051 program status word 00h 40 rfifo 0f4h gsc receive fifo x 41 rstat 0e8h gsc receive status 00h 42 sarl0 0a2h dma source address register (low) 0 x 43 sarh0 0a3h dma source address register (high) 0 x 44 sarl1 0b2h dma source address register (low) 1 x 45 sarh1 0b3h dma source address register (high) 1 x 46 sbuf 099h c8051 serial channel buffer (uart) x 47 scon 098h c8051 serial channel contr ol (uart) 00h 48 slottm 0b4h gsc gsc slot time 00h 49 sp 081h c8051 stack pointer 07h 50 tcdcnt 0d4h gsc transmit collision counter x 51 tcon 088h c8051 timer control 00h 52 tfifo 085h gsc transmit fifo x 53 th0 08ch c8051 timer (high) 0 00h 54 th1 08dh c8051 timer (high) 1 00h 55 tl0 08ah c8051 timer (low) 0 00h 56 tl1 08bh c8051 timer (low) 1 00h 57 tmod 089h c8051 timer mode 00h 58 tstat 0d8h gsc transmit status xx000100b ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 27 of 61 1 - 888 - 824 - 4184 table 12 . list of interrupts interrupt prio rity interrupt name priority symbol name enable symbol name priority address enable address vector address C enable all interrupts C ea C 0afh C 1 external interrupt 0 px0 ex0 0b8h 0a8h 03h 2 gsc receive valid pgsrv egsrv 0f8h 0c8h 2bh 3 timer 0 overfl ow pt0 et0 0b9h 0a9h 0bh 4 gsc receive error pgsre egsre 0f9h 0c9h 33h 5 dma channel 0 done pdma0 edma0 0fah 0cah 3bh 6 external interrupt 1 px1 ex1 0bah 0aah 13h 7 gsc transmit valid pgstv egstv 0fbh 0cbh 43h 8 dma channel 1 done pdma1 edma1 0fch 0cc h 53h 9 timer 1 overflow pt1 et1 0bbh 0abh 1bh 10 gsc transmit error pgste egste 0fdh 0cdh 4bh 11 uart transmit/receive ps es 0bch 0ach 23h 5.2 register set descriptions the following are detailed descriptions for the ia80c152 register set. this register set is the same for all versions of the ia80c152. there is no difference between the ia80c152 register set and the register set for the original device. in addition to the registers listed below, there are four banks of eight general purpose registers (r 0 through r7) which reside within internal ram space. selection of these register banks is controlled through the program status word (psw). the register descriptions are listed in alphanumeric order. the asterisk (*) indicates the register is bit addres sable. 5.2.1 a* (0e0h) accumulator register used for various memory, arithmetic, and logic operations. 5.2.2 adr0,1,2,3 (095h, 0a5h, 0b5h, 0c5h) address match registers contain the values which determine which data will be accepted as valid by the gsc. if using 8 bit addressing mode a match with any of the four registers will cause the data to be accepted. if using 16 bit addressing mode a match with the pairs adr1 and adr0 or adr3 and adr2 will cause the data to be accepted. a received address of all 1s will be acc epted regardless of whether the address mode is 16 bit or 8 bit. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 28 of 61 1 - 888 - 824 - 4184 5.2.3 amsk0,1 (0d5h, 0e5h) address match mask registers are used to set the corresponding bit in address match registers to dont care. setting the bit to a one in the amsk register sets the corre sponding bit in the adr register to dont care. 5.2.4 b* (0f0h) the b register used for multiply and divide instructions. may also be used as a general purpose register. 5.2.5 baud (094h) contains the value to be used by the baud rate determining equation. the valu e written to baud will actually be stored in a reload register. when the baud register contents are decremented to 00h the baud register will be reloaded from the reload register. reading the baud register yields the current baud rate timer value. a rea d during a gsc operation may not give the current value because the value in baud could decrement after it is read and before the read value can be stored in its destination. baud rate = fosc/((baud + 1)*8) 5.2.6 bcrl0, bcrh0 (0e2h, 0e3h) byte count register lo w and high bytes for dma channel 0. the two registers provide a 16 - bit value representing the number of dma transfers via channel 0. valid count range is from 0 to 65535. 5.2.7 bcrl1, bcrh1 (0f2h, 0f3h) byte count register low and high bytes for dma channel 1. the two registers provide a 16 - bit value representing the number of dma transfers via channel 1. valid count range is from 0 to 65535. 5.2.8 bkoff (0c4h) an 8 bit count down timer with a clock period equal to one slot time. a user may read the register, but the register is clocked asynchronously to the cpu so invalid data can result. writing to bkoff will have no effect. 5.2.9 darl0, darh0 (0c2h, 0c3h) destination address register low and high bytes for dma channel 0. the two registers provide a 16 - bit value repr esenting the address of the destination for a dma transfer via channel 0. valid address range is from 0 to 65535. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 29 of 61 1 - 888 - 824 - 4184 5.2.10 darl1, darh1 (0d2h, 0d3h) destination address register low and high bytes for dma channel 1. the two registers provide a 16 - bit value repres enting the address of the destination for a dma transfer via channel 1. valid address range is from 0 to 65535. 5.2.11 dcon0,1 (092h, 093h) dcon0 and dcon1 control dma channel 0 or 1, respectively. each bit in these 8 - bit registers control the dma transfer as d escribed in table 13 . table 13 . dcon0,1 register 7 6 5 4 3 2 1 0 das ida sas isa dm tm done go bit [ 7 ] das this bit in conjunction with ida determine s the destination address space. bit [6] ida if ida is set to 1 then the destination address is automatically incremented after the transfer of each byte. das ida destination auto - increment 0 0 external ram n o 0 1 external ram yes 1 0 sfr no 1 1 internal ram yes bit [5] sas this bit in conjunction with isa determine s the source address space. bit [4 ] isa if isa is set to 1 , the source address is automatically incremented after the transfer of each by te. sas isa source auto - increment 0 0 external ram no 0 1 external ram yes 1 0 sfr no 1 1 internal ram yes bit [3] dm if this bit is set to 1 , the dma channel operates in demand mode. in this mode the dma is initiated by either an external signal or by a serial port flag depending on the value of the tm bit. if the dm bit is set to 0 , dma is initiated by setting the go bit. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 30 of 61 1 - 888 - 824 - 4184 bit [2] tm if dm is 1 , tm selects if dma is initiated by an external signal (tm=1) or by a serial port bit (tm=0). if dm i s 0 , tm selects whether dma transfers are in burst mode (tm=1) or in alternate cycles mode (tm=0). dm tm mode 0 0 alternate cycles 0 1 burst 1 0 lsc/gsc interrupt demand 1 1 external interrupt demand bit [1] done this bit indicates that the dma op eration has completed. it also causes an interrupt. this bit is set to 1 when bcrn equals 0 and is set to 0 when the interrupt is vectored. the user can also set and clear this bit. bit [0] go if this bit is set to 1 , it enables the dma channel. 5.2.12 dpl , dph (082h, 083h) dptr, or the D data pointer consists of the two 8 - bit registers, dpl and dph. the dptr must be used for accesses to external memory requiring 16 - bit addresses. 5.2.13 gmod (084h) an 8 - bit register that controls the gsc modes as described in table 14 . table 14 . gmod register 7 6 5 4 3 2 1 0 xtclk m1 m0 al ct pl1 pl0 pr bit [7] xtclk this bit enables the use of an external transmit clock. a 1 enables the external clock (input on port 1, bit 3), a zero enables the internal baud rate generator. bits [6 C 5 ] m1, m0 these bits are the backoff mode and test mode select bits as defined in the following table. m1 m0 mode 0 0 normal 0 1 raw transmit 1 0 raw receive 1 1 alternate backoff in raw receive mode the transmitter operates normally. the receiver operates normally except that all the bytes following the bof are loaded into the receive fifo including the crc. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 31 of 61 1 - 888 - 824 - 4184 in the raw transmit mode the receiver operates as normal and zero bit detection is performed in sdlc mode. the transmit output is internally connected to the receiver input for loopback testing. data transmitted is done so without a preamble, flag or zero bit insertion and without a crc. in the alternate backoff mode the backoff is modified so it is delayed until the end of the ifs. since the ifs time is generally longer than the slot time this should help to prevent co llisions. bit [4 ] al this bit determines the address length used. if set to a 1, the 16 - bit addressing is used. if set to a 0, the 8 bit addressing is used. bit [3 ] ct this bit determines the crc type used. if set to a 1, the 32 - bit autodin ii - 32 is used. if set to a 0 , the 16 bit crc - ccitt is used. bit s [2 C 1 ] pl0, pl 1 preamble length: pl1 pl0 preamble length in bits 0 0 0 0 1 8 1 0 32 1 1 64 the length note d in the table includes the two - bit bof in csma/cd mode but not the sdlc flag. zero length preamble is n ot compatible with csma/cd mode. bit [ 0 ] pr i f set to a 1, the gsc is in sdlc mode. if set to a 0, the gsc is in csma/cd mode. 5.2.14 ie* (0a8h) the interrupt enable register allows the software to select which interrupts are enabled as shown in table 15 . if a bit is 0, the interrupt is disabled. if a bit is 1, the interrupt is enabled. table 15 . ie* register 7 6 5 4 3 2 1 0 ea reserved reserved es et1 ex1 et0 ex0 bit [7] ea enable all interrupts. this bit globally enables or d isables all interrupts regardless of the state of the individual bits. bit [6] reserved. bit [5] reserved. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 32 of 61 1 - 888 - 824 - 4184 bit [4 ] es enable or disable serial port interrupt. bit [3 ] et1 enable or disable timer 1 overflow interrupt. bit [2 ] ex 1 enable or disable ext ernal interrupt 1. bit [1 ] et0 enable or disable timer 0 overflow interrupt. bit [0 ] ex0 enable or disable external interrupt 0. 5.2.15 ien1* (0c8h) the interrupt enable number 1 register allows the software to select which interrupts are enabled as shown in table 16 . if a bit is 0, the interrupt is disabled. if a bit is 1, the interrupt is enabled. table 16 . ien1* register 7 6 5 4 3 2 1 0 reserved reserved egste edma1 egstv edma0 egsre egsrv bit [7 ] reserved. bit [6 ] reserved. b it [5 ] egste enable or disable gsc transmit error interrupt. bit [ 4 ] edma1 enable or disable dma channel 1 interrupt. bit [3 ] egstv enable or disable gsc transmit valid interrupt. bit [2 ] edma0 enable or disable dma channel 0 interrupt. bit [1 ] egsre enable o r disable gsc receive error interrupt. bit [0 ] egsrv enable or disable gsc receive valid interrupt. 5.2.16 ifs (0a4h) the interframe spacing register determines the number of bit times between transmitted frames in both csma/cd and sdlc. only even bit times ca n be used. the number written to this register is divided by two and loaded into the seven most significant bits. an interframe space is created by counting down this seven bit number twice. the value read from this register is the current count value i n the upper seven bits and the first or second count down in the lsb. a 1 indicates the first count down and a 0 indicates the second count down. the value may not be valid because the register is clocked asynchronously to the cpu. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 33 of 61 1 - 888 - 824 - 4184 5.2.17 ip* (0b8h) the interru pt priority register allows the software to select which interrupts have a higher than normal priority. if a bit is 0, the interrupt has normal priority. if a bit is 1, the interrupt has a higher priority. when multiple bits are set to higher priority, interrupts are resolved in the same order as their normal priority setting (see table 17) . table 17 . ip* register 7 6 5 4 3 2 1 0 reserved reserved reserved ps pt1 px1 pt0 px0 bit [7 ] reserved. bit [6 ] reserved. bit [5 ] reserve d. bit [4 ] ps set normal or high priority level for serial port interrupt. bit [3 ] pt1 set normal or high priority level for timer 1 overflow interrupt. bit [2 ] px1 set normal or high priority level for external interrupt 1. bit [1 ] pt0 set normal or high priority level for timer 0 overflow interrupt. bit [0 ] px0 set normal or high priority level for external interrupt 0. 5.2.18 ipn1* (0f8h) the interrupt priority number 1 register allows the software to select which interrupts have a higher than normal priority. if a bit is 0, the interrupt has normal priority. if a bit is 1, the interrupt has a higher priority. when multiple bits are set to higher priority, interrupts are resolved in the same order as their normal priority setting (see table 18) . tab le 18 . ip n1 * register 7 6 5 4 3 2 1 0 reserved reserved pgste pdma1 pgstv pdma0 pgsre pgsrv bit [7 ] reserved. bit [6 ] reserved. bit [5 ] pgste set normal or high priority level for gsc transmit error interrupt. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 34 of 61 1 - 888 - 824 - 4184 bit [4 ] pdma1 set normal or high priority level for dma channel 1 interrupt. bit [3 ] pgstv set normal or high priority level for gsc transmit valid interrupt. bit [2 ] pdma0 set nor mal or high priority level for dma channel 0 interrupt. bit [1 ] pgsre set normal or high priority level for gsc receive error interrupt. bit [0 ] pgsrv set normal or high priority level for gsc receive valid interrupt. 5.2.19 myslot (0f5h) register that contro ls the slot address for the devices as well as the type of jam used and which backoff algorithm is used during a collision (see table 19) . table 19 . myslot register 7 6 5 4 3 2 1 0 dcj dcr sa5 sa4 sa3 sa2 sa1 sa0 bit [7 ] dcj a 1 selects dc type jam. a 0 selects ac type jam. bit [6 ] dcr the deterministic collision resolution register determines which resolution algorithm to use. setting this bit to a 1 selects the deterministic resolution algorithm. the user must initializ e tcdcnt with the maximum number of slots that are appropriate for the system. to disable the pbrs this register must be set to all 1s. if dcr is cleared to 0 then a random slot assignment is used. the type of random backoff used is selected by bits m1, m0 of the gmod register. bits [5 C 0 ] sa5 C sa 0 the six - slot address bits determine not only the address but also the priority. addresses 0 through 63 are available with 63 having the highest priority and 1 the lowest. an address of 0 will prevent a station from transmitting during the collision res olution period. 5.2.20 p 0*, p1*, p2*, p3*, p4*, p5, p6 (080h, 090h, 0a0h, 0boh, 0c0h, 091h, 0a1h) these registers are for i/o as defined in table 20 . most registers have a dual function. p5 and p6 are not bit addressable and are only available in the jb and jd versions of the ic. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 35 of 61 1 - 888 - 824 - 4184 table 20 . p0*, p1*, p2*, p3*, p4*, p5, p6 register port bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 function multiplexed address/data bit address 087h 086h 085h 084h 083h 082h 081h 080h p1 function C hldan hldn rxcn txcn denn gtxd grxd bit address 097h 096h 095h 094h 093h 092h 091h 090h p2 function address and user defined bit address 0a7h 0a6h 0a5h 0a4h 0a3h 0a2h 0a1h 0a0h p3 function rdn wrn t1 t0 int1n int0n txd rxd bit address 0b7h 0b6h 0 b5h 0b4h 0b3h 0b2h 0b1h 0b0h p4 function user defined bit address 0c7h 0c6h 0c5h 0c4h 0c3h 0c2h 0c1h 0c0h p5 function user defined bit address 091h p6 function user defined address 0a1h 5.2.21 pcon (087h) the power control register controls the power d own and idle states of the ia80c152 as well as various uart, gsc, and dma functions as defined in table 21 . table 21 . pcon register 7 6 5 4 3 2 1 0 smod arb req garen xrclk gfien pd idl bit [7 ] smod doubles the baud rate of t he uart if the bit is set to 1. bit [6 ] arb the dma (both channels) is put into arbiter mode if the bit is set to 1. bit [5 ] req the dma (both channels) is put into requ ester mode if the bit is set to 1. bit [4 ] garen the gsc auxiliary receive enable allows the gsc to receive back - to - back sdlc frames by setting the bit to 1. this bit has no effect in csma mode. bit [3 ] xrclk setting this bit enables the external receive clock to be used by the receiver portion of the gsc. bit [2 ] gfien the gsc fl ag idle enable bit generates idle flags between transmitted sdlc frames when this bit is set to a 1. this bit has no effect in csma mode. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 36 of 61 1 - 888 - 824 - 4184 bit [ 1 ] pd the power down bit puts the ia80c152 into the power down power saving mode by setting this bit to a 1. b it [0 ] idl the idle bit puts the ia80c152 into the idle power saving mode by setting this bit to a 1. 5.2.22 prbs (0e4h) this register contains the pseudo - random number to be used in the csma/cd backoff algorithm. the number is generated by using a feedback sh ift register clocked by the cpu phase clocks. writing all 1s to this register will cause the register to freeze at all 1s. writing any other value to it will cause it to start again. a read of this register will not always give the seed value due to the register being clocked by the cpus phase clocks. 5.2.23 psw* (0d0h) the program status word register provides arithmetic and other microcontroller status as well as control for the selection of register banks 0 through 4 (see table 22) . table 22 . psw* register 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov reserved p bit [7 ] cy carry flag set to 1 if an instruction execution results in a carry/borrow from/to bit 7. bit [6 ] ac auxiliary carry flag set to 1 if an instruction execution results in a carry/borrow from/to bit 3. bit [5 ] f0 flag 0 available for user defined general purpose. bits [4 C 3 ] rs1, rs0 register bank select 1 bit and register bank select 0 bit in combination define the current register bank to be used by the microprocesso r. see table below. register bank rs1 rs0 register bank addresses 0 0 0 00h - 07h 1 0 1 08h - 0fh 2 1 0 10h - 17h 3 1 1 18h - 1fh bit [2 ] ov the overflow bit indicates an arithmetic overflow when set to a 1. bit [1 ] reserved. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 37 of 61 1 - 888 - 824 - 4184 bit [0 ] p parity flag set o r cleared by the hardware each instruction to indicate odd or even number of 1s in the accumulator. 5.2.24 rfifo (0f4h) this is a three - byte buffer which points to the oldest data in the buffer. the buffer is loaded with receive data every time the gsc receiver receives a new byte of data. 5.2.25 rstat* (0e8h) this register provides status of the gsc receiver as defined in table 23 . table 23 . rstat* register 7 6 5 4 3 2 1 0 ovr rcabt ae crce rdn rfne gren haben bit [7 ] ovr this bit is set by the gsc to indicate that the receive fifo was full and then new data was shifted into it. ae and /or crce may also be set. this flag is cleared by the user. bit [6 ] rcabt this bit is set by the gsc when a collision is detected afte r data has been loaded into the receive fifo in csma/cd mode. in sdlc mode this bit indicates that 7 consecutive 1s were detected before an end flag but after data was loaded into the receive fifo. ae may also be set. bit [ 5 ] ae this bit is set by the gsc in csma/cd mode to indicate that the receiver shift register is not full and the crc is bad when the eof was detected. if the crc is correct ae will not be set and a misalignment will be assumed to be caused by D dribble bits as the line went idle. i n sdlc mode ae is set if a non - byte aligned flag is received. crce may also be set. bit [4 ] crce this bit is controlled by the gsc and if set indicates that a properly aligned frame was received with a mismatched crc. bit [3 ] rdn this bit is controlled by the gsc and if set indicates a successful receive operation has occurred. this bit will not be set if a crc, alignment, abort, or fifo overrun error occurred. bit [2 ] rfne this bit if set indicates that the receive fifo is not empty. this flag is controlled by the gsc. if all the data is read from the fifo the gsc will clear the bit. bit [1 ] gren when this bit is set the receiver is enabled to accept incoming frames. rfifo should be cleared before setting this bit by reading rfifo until rfne = 0. this should be done because setting gren to a 1 clears rfifo. it takes twelve clock cycles ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 38 of 61 1 - 888 - 824 - 4184 for the status of rfne to be updated after a read of rfifo. setting gren also clears rdn, crce, ae and rcabt. gren is cleared by hardware at the end of a reception or if receive errors are encountered. the user is responsible for setting this bit to a 1. the user or the gsc can set this bit to a 0. in csma/cd mode the status of gren has no effect on whether the receiver detects a collision because the receiver always monitors the receive pin. bit [ 0 ] haben the hardware based acknowledge enable when set to a 1 enables this feature. 5.2.26 sarl0, sarh0 (0a2h, 0a3h) source address register low and high bytes for dma channel 0. the two registers provide a 16 - bit value representing the address of the source for a dma transfer via channel 0. valid address range is from 0 to 65535. 5.2.27 sarl1, sarh1 (0b2h, 0b3h) source address register low and high bytes for dma channel 1. the two registers provide a 16 - bit value representing the address of the source for a dma transfer vi a channel 1. valid address range is from 0 to 65535. 5.2.28 sbuf (099h) writes to this register load the transmit register, and reads access the receive register of the lsc. 5.2.29 scon* (098h) this register controls the set up of the uart as defined by table 24 . table 24 . scon * register 7 6 5 4 3 2 1 0 sm0 sm1 sm2 ren tb8 rb8 ti ri bit s [ 7 C 6 ] sm0, sm1 the combination of these 2 bits controls the mode and type of baud rate. mode sm0 sm1 description baud rate 0 0 0 shift register (osc. fre q.)/12 1 0 1 8 - bit uart variable 2 1 0 9 - bit uart (osc. freq.)/64 or (osc. freq.)/32 3 1 1 9 - bit uart variable ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 39 of 61 1 - 888 - 824 - 4184 bit [ 5 ] sm2 when this bit is set and the uart mode is 1, ri will not be activated unless a valid stop bit is received. when this bit is s et and the uart mode is 2 or 3, ri will not be activated if the 9th bit is 0. in mode 0 sm2 should be set to 0. bit [ 4] ren setting this bit enables the uart to receive. clearing this bit disables uart reception. bit [ 3 ] tb8 in modes 2 and 3, the val ue of this bit is transmitted during the 9th bit time. this bit is set or cleared by software. bit [ 2 ] rb8 in modes 2 and 3, this bit is the value of the 9th bit that was received by the uart. in mode 1 with sm2 = 1, this bit is the value of the stop b it received by the uart. in mode 0 rb8 is not used. bit [ 2 ] ti transmit interrupt flag set by hardware at the end of the 8th bit in mode 0 or at the beginning of the stop bit in modes 1, 2, or 3. this bit must be cleared by software to clear the interr upt. bit [ 0 ] ri receive interrupt flag set by hardware at the end of the 8th bit in mode 0 or halfway through the stop bit in modes 1, 2, or 3. this bit must be cleared by software to clear the interrupt. 5.2.30 slottm (0b4h) determines the length of the slot time in csma/cd mode. a slot time equals slottm * (1/ baud rate). reads from this location are unreliable because this register is clocked asynchronously to the cpu. loading a value of 0 results in a slot time of 256 bit times. 5.2.31 sp (081h) this register is the stack pointer. its value points to the memory location that is the beginning of the stack. 5.2.32 tcdcnt (0d4h) if probabilistic csma/cd is used this register contains the number of collisions. the user must clear this register before transmitting a new fr ame so the gsc can distinguish between a new frame and the retransmit of a frame. in deterministic backoff mode tcdcnt is used to hold the maximum number of slots. 5.2.33 tcon* (088h) this register controls the operation of the timers 0 and 1 and external interr upts 0 and 1 as defined by table 25 . ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 40 of 61 1 - 888 - 824 - 4184 table 25 . tcon * register 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit [ 7 ] tf1 timer overflow 1 interrupt flag set by hardware when timer 1 overflows. hardware clears this flag when the processor vectors to the interrupt service routine. bit [ 6 ] tr1 timer run 1 flag set by software to turn on timer 1 and cleared by software to t urn off timer 1. bit [ 5 ] tf0 timer overflow 0 interrupt flag set by hardware when timer 0 overflows. hardware clears this flag when the processor vectors to the interrupt service routine. bit [ 4 ] tr0 timer run 0 flag set by software to turn on timer 0 and cleared by software to turn off timer 0. bit [ 3 ] ie1 interrupt external 1 flag set by hardware when an edge is detected on external interrupt 1. hardware clears this flag when the processor vectors to the interrupt service routine. bit [ 2 ] it1 in terrupt type 1 flag is set by software to specify a falling edge triggered interrupt for external interrupt 1. the flag is cleared by software to specify a low level triggered interrupt for external interrupt 1. bit [ 1 ] ie0 interrupt external 0 flag set by hardware when an edge is detected on external interrupt 0. hardware clears this flag when the processor vectors to the interrupt service routine. bit [ 0 ] it0 interrupt type 0 flag is set by software to specify a falling edge triggered interrupt for external interrupt 0. the flag is cleared by software to specify a low level triggered interrupt for external interrupt 0. 5.2.34 tf ifo (085h) this is the 3 byte buffer used for storing gsc transmit data. if ten is set to a 1 transmission begins as soon as data is written to tfifo. 5.2.35 th0, tl0 (08ch, 08ah) these registers provide the high byte (th0) and low byte (tl0) values for timer 0. these registers may be used together or separately depending on timer 0 mode bits. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 41 of 61 1 - 888 - 824 - 4184 5.2.36 th1, tl1 (08dh, 08bh) these registers provid e the high byte (th0) and low byte (tl0) values for timer 0. these registers may be used together or separately depending on timer 0 mode bits. 5.2.37 tmod (089h) this register controls the set up and modes of timers 0 and 1 as defined by table 26 . table 26 . tmod register 7 6 5 4 3 2 1 0 timer 1 timer 0 gate c/tn m1 m0 gate c/tn m1 m0 bit s [ 7,3 ] gate when this bit is set, timers/counters may be turned on or off by the corresponding external interrupt being high, if the appropriate tr bit is set. when this bit is cleared, timers/counters may only be turned on or off by the appropriate tr bit. bit s [ 6 ,2 ] c/tn counter/timer flag. set by software for counter operation, cleared by software for timer operation. bit [ 5,4,1,0 ] m1, m0 set the mode of the timers/counters as defined by the table below. mode m1 m0 description 0 0 0 8 - bit timer (thx) with 5 - bit prescalar (tlx) 1 0 1 16 - bit timer/counter (thx cascaded with tlx) 2 1 0 8 - bit auto reload timer/counter (thx), reload value (thx) 3 1 1 one 8 - bit timer/counter (tl0) controlled by timer 0 control bits. one 8 - bit timer/counter (th0) controlled by t imer 1 control bits. timer 1 is stopped. 5.2.38 tstat* (0d8h) this register provides status of the gsc transmitter as defined by table 27 . table 27 . tmod register 7 6 5 4 3 2 1 0 lni noack ur tcdt tdn tfnf ten dma bit [ 7 ] lni the gsc sets this bit to indicate that the receive line is idle. in csma/cd mode lni is set if grxd remains high for ~ 1.6 bit times. lni is cleared after a transition on grxd. in sdlc node lni is set if 15 consecutive ones are received. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 42 of 61 1 - 888 - 824 - 4184 bit [ 6 ] noack the gsc sets this bit to indicate that an acknowledge was not received for the previous frame. this bit will be set only if haben is set and no acknowledge is received before the end of the ifs. noack will not be set following a broadcast or a multi - c ast packet. bit [ 5 ] ur the gsc sets this bit to indicate that in dma mode the last bit was shifted out of the transmit register and that the dma byte count did not equal 0. when this occurs the transmitter stops without sending the crc and the end flag. bit [ 4 ] tcdt the gsc sets this bit to indicate that the transmission stopped due to a collision. the bit is set by a collision occurring during the data, the crc or if there are more than 8 collisions. bit [ 3 ] tdn the gsc sets this bit to indicate th at a frame transmission completed successfully. if haben is set, tdn will not be set until the end of the ifs so that the acknowledge can be checked. tdn will not be set if an acknowledge is expected but not received. an acknowledge will not be expected after a broadcast or a multi - cast packet. bit [ 2 ] tfnf if this bit is a 1 tfifo is not full and new data may be written to it. bit [ 1 ] ten when ten is set it will cause tdn, ur, tcdt and noack to be reset and the tfifo to be cleared. the transmitter will clear ten after a successful transmission, a collis ion during data, crc or end flag. the user sets the bit and the user of the gsc can clear the bit. if the bit is cleared during a transmission the transmit pin goes to a high level. this is the method used to send an abort character in sdlc. den is als o forced to a high level. an end of transmission occurs whenever the tfifo is emptied. bit [ 0 ] dma if this bit is set it indicates that the dma channels are used to service the rfifo and tfifo and that gsc interrupts occur on tdn and rdn. if set it also enables ur to become set. if this bit is cleared it indicates that the gsc is operating in normal mode and interrupts occur on tfnf and rfne. 5.3 power conservation modes there are 2 power conservation modes identified as idle mode and power down mode. the ia80c152 pins will have values according to the table 28 below. idle mode is entered through softwa re control of the pcon register. idle halts processor execution and the dma. the gsc continues to operate to the extent that it can without the processor or dma servicing its requests. idle mode is exited upon receipt of any enabled interrupt or invokin g a hardware reset. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 43 of 61 1 - 888 - 824 - 4184 power down mode is entered through software control of the pcon register. power down disables the oscillator causing all functions to stop. ram data is maintained because power is not removed from the device. the only way to exit pow er down mode is to invoke a hardware reset. table 28 . power conservation modes mode program fetch ale psenn epsenn a port 0 port 1 port 2 port 3 port 4 port 5 a port 6 a idle p0, p2 1 1 1 float data addr. data data data data p5, p 6 a 1 1 1 data data data data data 0ffh addr. power down p0, p2 0 0 1 float data data data data data data p5, p6 a 0 1 0 data data data data data 0ffh 0ffh a jb and jd versions only . 5.4 oscillator pins there are 2 methods for providing a clock to the ia80c1 52. one method is to provide a crystal oscillator and the other method is to provide an external clock source. when providing a crystal oscillator, the xtal1 pin is the input and xtal2 is the output. the min and max crystal frequencies are 3.5 and 16.5 mhz, respectively. when providing an external clock source, xtal1 is the input and xtal2 has no connection. duty cycle does not matter to the device, however, the external clock source requires a minimum pulse width of 20 ns. figures 6 through 13 present the external program memory read cycle, the external data memory read cycle, the external data memory write cycle, the external clock drive waveform, the shift register mode timing waveforms, the gsc receiver timings (internal baud rate generator), the gsc transmit timings (internal baud rate generator), the gsc timings (external clock) respectively. tables 29 through 32 present the external clock drive, the local serial channel timing shift register mode, the global serial port timing internal baud rate g enerator, and the global serial port timing external clock, respectively. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 44 of 61 1 - 888 - 824 - 4184 figure 6 . external program memory read cycle figure 7 . external data memory read cycle ? ale psenn/epsenn port0/port5 port2/port6 a0 - a7 instr in a0 - a7 a8 - a15 a8 - a15 a8 - a15 tlhll tllpl tplp h tavll tlliv tpliv tplaz tllax tpxix tpxiz taviv ale psenn rdn port 0 port 2 a0 - a7 from r or dpl data in a0 - a7 from pcl instr. in p2. 0 C p2.7 or a8 C a15 from dph a8 C a15 from pch twhlh tlldv tllwl trlrh tavll tllax trldv trlaz trhdx trhdz tavdv tavwl
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 45 of 61 1 - 888 - 824 - 4184 figure 8 . external data memory write cycle ? ale psenn wrn port0 port2 a0 - a7 from r or dpl data out a0 - a7 from pcl instr. in p2.0 - p2.7 or a8 - a15 from dph a8 - a1 5 from pch p2.0 - p2.7 or a8 - a15 from dph twhlh tllwl twlwh tqvwx tavll tllax twhqx tavwl
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 46 of 61 1 - 888 - 824 - 4184 table 29 . external clock drive symbol parameter min max units 1/tclcl oscillator frequency 0 16.5 mhz tchcx high time 2 0 C ns tclcx low time 20 C ns tclch rise time C tbd ns tchcl fall time C tbd ns figure 9 . external clock drive waveform table 30 . local serial channel timing shift regis ter mode symbol parameter 16.5 mhz variable oscillator units min max min max txlxl serial port clock cycle time 727 C 12tclcl C ns tqvxh output data setup to clock rising edge 570 C 10tclcl - 133 C ns txhqx output data hold after clock rising edge 10 C 2tclcl - 117 C ns txhdx input data hold after clock rising edge 0 C 0 C ns txhdv clock rising edge to input data valid C 480 C 10tclcl - 133 ns ? v cc - 0.5 0.7 v cc 0.2 v cc - 0.1 0.45v tchcl tclcx tchcx tclch tclcl
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 47 of 61 1 - 888 - 824 - 4184 figure 10 . shift register mode timing wavefor ms table 31 . global serial port timing internal baud rate generator symbol parameter 16.5 mhz (baud = 0) variable oscillator unit min max min max hbtjr allowable jitter on the receiver for 1/2 bit time (manchester enco ding only) C 0.06 C (0.125 (baud + 1) 8tclcl) - 25ns s fbtjr allowable jitter on the receiver for one full bit time (nrzi and manchester) C 0.06 C (0.125 (baud + 1) 8tclcl) - 25ns s hbtjt jitter of data from transmitter for 1/2 bit time (manche ster encoding only) C 10 C 10 ns fbtjt jitter of data from transmitter for one full bit time (nrzi and manchester) C 10 C 10 ns drtr data rise time for receiver C tbd C 20.00 ns dftr data fall time for receiver C tbd C 20.00 ns ? valid valid valid valid txlxl txhq x tqvxh txhd x txhdv | 0 | | | | | | | | | 1 2 3 4 5 6 7 8 |____________ | |_________| ^ | write to sbuf clear r1 ^ | ^ | ^ | set t1 set r1 instruction ale clock output_data input_data 0 1 2 3 4 5 6 7 7 valid valid valid valid valid
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 48 of 61 1 - 888 - 824 - 4184 figure 11 . gsc receiver timings (internal baud rate generator) figure 12 . gsc transmit timings (internal baud rate generator) ? manchester nrzi bt hbtjr hbtjr fbtjr fbtjr fbtjr fbtjr grxd grxd manchester nrzi bt hbtjt fbtjt fbtjt fbtjt fbtjt hbtjt gtxd gtxd
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 49 of 61 1 - 888 - 824 - 4184 table 32 . global serial port timing external clock symbol parameter 16.5 mhz variable oscillator unit min max min max 1/ecbt gsc frequency with an external clock C 2.4 C fosc 0.145 mhz ech external clock high 170 C 2tclcl + 45 C ns ecl exte rnal clock low 170 C 2tclcl + 45 C ns ecrt external clock rise time C tbd C 20 ns ecft external clock fall time C tbd C 20 ns ecdvt external clock to data valid out transmit (to external clock negative edge) C 33 C 150 ns ecdht external clock to data h old transmit (to external clock negative edge) 3 C 0 C ns ecdsr external clock to data set - up receiver (to external clock positive edge) 55 C 45 C ns ecdhr external clock to data hold receiver (to external clock positive edge) 63 C 50 C ns figure 13 . gsc timings (external clock) ? external_clock transmit_data external_clock receive_data ecbt ecbt ecl ech ecdht ecdvt ecdsr ecdhr
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 50 of 61 1 - 888 - 824 - 4184 6. instruction set summary table table 33 provides a summary of the instruction set organized by hexadecimal opcode. please refer to the original intel data book for individual instruction set detail s. table 33 . instruction set summary opcode mnemonic 00 h nop 01 h ajmp addr11 02 h ljmp addr16 03 h rr a 04 h inc a 05 h inc direct 06 h inc @r0 07 h inc @r1 08 h inc r0 09 h inc r1 0a h inc r2 0 b h inc r3 0c h inc r4 0d h inc r5 0e h inc r6 0f h inc r7 10 h jbc bit,rel 11 h acall addr11 12 h lcall addr16 13 h rrc a 14 h dec a 15 h dec direct 16 h dec @r0 17 h dec @r1 18 h dec r0 19 h dec r1 1a h dec r 2 1b h dec r3 1c h dec r4 1d h dec r5 1e h dec r6 1f h dec r7 20 h jb bit.rel 21 h ajmp addr11 22 h ret 23 h rl a 24 h add a,#data 25 h add a,direct 26 h add a,@r0 27 h add a,@r1 28 h add a,r0 ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 51 of 61 1 - 888 - 824 - 4184 table 33 . instruc tion set summary (continued) opcode mnemonic 29 h add a,r1 2a h add a,r2 2b h add a,r3 2c h add a,r4 2d h add a,r5 2e h add a,r6 2f h add a,r7 30 h jnb bit.rel 31 h acall addr11 32 h reti 33 h rlc a 34 h addc a,#data 35 h addc a,direct 36 h addc a,@r0 37 h addc a,@r1 38 h addc a,r0 39 h addc a,r1 3a h addc a,r2 3b h addc a,r3 3c h addc a,r4 3d h addc a,r5 3e h addc a,r6 3f h addc a,r7 40 h jc rel 41 h ajmp addr11 42 h orl direct,a 4 3 h orl direct,#data 44 h orl a,#data 45 h orl a,direct 46 h orl a,@r0 47 h orl a,@r1 48 h orl a,r0 49 h orl a,r1 4a h orl a,r2 4b h orl a,r3 4c h orl a,r4 4d h orl a,r5 4e h orl a,r6 4f h orl a,r7 50 h jnc rel 51 h acall addr1 1 52 h anl direct,a 53 h anl direct,#data 54 h anl a,#data 55 h anl a,direct 56 h anl a,@r0 ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 52 of 61 1 - 888 - 824 - 4184 table 33 . instruction set summary (continued) opcode mnemonic 57 h anl a,@r1 58 h anl a,r0 59 h anl a,r1 5a h anl a,r2 5b h anl a,r3 5c h a nl a,r4 5d h anl a,r5 5e h anl a,r6 5f h anl a,r7 60 h jz rel 61 h ajmp addr11 62 h xrl direct,a 63 h xrl direct,#data 64 h xrl a,#data 65 h xrl a,direct 66 h xrl a,@r0 67 h xrl a,@r1 68 h xrl a,r0 69 h xrl a,r1 6a h x rl a,r2 6b h xrl a,r3 6c h xrl a,r4 6d h xrl a,r5 6e h xrl a,r6 6f h xrl a,r7 70 h jnz rel 71 h acall addr11 72 h orl c, bit 73 h jmp @a+dptr 74 h mov a,#data 75 h mov direct,#data 76 h mov @r0,#data 77 h mov @r1,#data 78 h mov r0.#data 79 h mov r1.#data 7a h mov r2.#data 7b h mov r3.#data 7c h mov r4.#data 7d h mov r5.#data 7e h mov r6.#data 7f h mov r7.#data 80 h sjmp rel 81 h ajmp addr11 82 h anl c,bit 83 h movc a,@a+pc 84 h div ab ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 53 of 61 1 - 888 - 824 - 4184 table 33 . instruction set summary (continued) opcode mnemonic 85 h mov direct,direct 86 h mov direct,@r0 87 h mov direct,@r1 88 h mov direct,r0 89 h mov direct,r1 8a h mov direct,r2 8b h mov direct,r3 8c h mov direct,r4 8d h mov direct,r5 8e h mov direct,r6 8f h mov direct,r7 90 h mov dptr,#data16 91 h acall addr11 92 h mov bit,c 93 h movc a,@a+dptr 94 h subb a,#data 95 h subb a,direct 96 h subb a,@r0 97 h subb a,@r1 98 h subb a,r0 99 h s ubb a,r1 9a h subb a,r2 9b h subb a,r3 9c h subb a,r4 9d h subb a,r5 9e h subb a,r6 9f h subb a,r7 a0 h orl c,bit a1 h ajmp addr11 a2 h mov c,bit a3 h inc dptr a4 h mul ab a5 h C a6 h mov @r0,direct a7 h mov @r1,direct a8 h mov r0,direct a9 h mov r1,direct aa h mov r2,direct ab h mov r3,direct ac h mov r4,direct ad h mov r5,direct ae h mov r6,direct af h mov r7,direct b0 h anl c,bit b1 h acall addr11 b2 h cpl bit ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 54 of 61 1 - 888 - 824 - 4184 table 33 . instruction set summary (c ontinued) opcode mnemonic b3 h cpl c b4 h cjne a,#data,rel b5 h cjne a,direct,rel b6 h cjne @r0,#data,rel b7 h cjne @r1,#data,rel b8 h cjne r0,#data,rel b9 h cjne r1,#data,rel ba h cjne r2,#data,rel bb h cjne r3,#data,rel bc h cjne r4,# data,rel bd h cjne r5,#data,rel be h cjne r6,#data,rel bf h cjne r7,#data,rel c0 h push direct c1 h ajmp addr11 c2 h clr bit c3 h clr c c4 h swap a c5 h xch a,direct c6 h xch a,@r0 c7 h xch a,@r1 c8 h xch a,r0 c9 h xch a, r1 ca h xch a,r2 cb h xch a,r3 cc h xch a,r4 cd h xch a,r5 ce h xch a,r6 cf h xch a,r7 d0 h pop direct d1 h acall addr11 d2 h setb bit d3 h setb c d4 h da a d5 h djnz direct,rel d6 h xchd a,@r0 d7 h xchd a,@r1 d8 h dj nz r0,rel d9 h djnz r1,rel da h djnz r2,rel db h djnz r3,rel dc h djnz r4,rel dd h djnz r5,rel de h djnz r6,rel ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 55 of 61 1 - 888 - 824 - 4184 table 33 . instruction set summary (continued) opcode mnemonic df h djnz r7,rel e0 h movx a,@dptr e1 h ajmp addr11 e2 h movx a,@r0 e3 h movx a,@r1 e4 h clr a e5 h mov a,direct e6 h mov a,@r0 e7 h mov a,@r1 e8 h mov a,r0 e9 h mov a,r1 ea h mov a,r2 eb h mov a,r3 ec h mov a,r4 ed h mov a,r5 ee h mov a,r6 ef h mov a,r7 f0 h movx @dptr,a f1 h acall addr11 f2 h movx @r0,a f3 h movx @r1,a f4 h cpl a f5 h mov direct,a f6 h mov @r0,a f7 h mov @r1,a f8 h mov r0,a f9 h mov r1,a fa h mov r2,a fb h mov r3,a fc h mov r4,a fd h mov r5,a fe h mov r6,a ff h mov r7,a ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 56 of 61 1 - 888 - 824 - 4184 7. ac char acteristics table 34 . external program and data memory characteristics symbol parameter 16.5 mhz variable oscillator unit min max min max 1/tclcl oscillator frequency 80c152ja/ jc 83c152ja/jc 83c152jb/jd C 16.5 C 16.5 mhz 8 0c152ja/jc - 1 83c152ja/ jc - 1 80c152jb/jd - 1 C 16.5 C 16.5 mhz tlhll ale pulse width 125 C 2tclcl+4 C ns tavll address valid to ale low 48 C tclcl - 8 C ns tllax address hold after ale low 60 C tclcl - 9 C ns tlliv ale low to valid instruction in C 232 C 4tcl cl - 35 ns tllpl ale low to psenn low 61 C tclcl C ns tplph psenn pulse width 186 C 3tclcl+4 C ns tpliv psenn low to valid instruction in C 172 C 3tclcl - 35 ns tpxix input instruction hold after psenn 0 C 0 C ns tpxiz input instruction float after psenn C 80 C tclcl - 7 ns taviv address to valid instruction in C 274 C 5tclcl - 43 ns tplaz psenn low to address float C 4 C C ns trlrh rdn pulse width 351 C 6tclcl - 13 C ns twlwh wrn pulse width 351 C 6tclcl - 13 C ns trldv rdn low to valid data in C 280 C 5tcl cl - 35 ns trhdx data hold after rdn 0 C 0 C ns trhdz data float after rdn C 62 C 2tclcl - 2 ns tlldv ale low to valid data in C 478 C 8tclcl - 34 ns tavdv address to valid data in C 542 C 9tclcl - 42 ns tllwl ale low to rdn or wrn low 179 181 3tclcl 3tclcl n s tavwl address to rdn or wrn low 236 C 4tclcl - 8 C ns tqvwx data valid to wrn transition 344 C tclcl - 7 C ns twhqx data hold after wrn 41 C tclcl+3 C ns trlaz rdn low to address float C 3 C 9 ns twhlh rdn or wrn high to ale high 61 61 tclcl tclcl ns ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 57 of 61 1 - 888 - 824 - 4184 8. innovasic/ intel part number cross - reference table table 35 show s innovasic part numbers cross - referenced with the corresponding intel part number . table 35 . innovasic/ intel part number cross - reference innovasic part number intel part number package type temperature grades ia80c152ja/jc - plc68i - r - 01 (rohs - compliant package) n80c152a n80c152ja n80c152ja1 n80c152jc n80c152jc1 68 lead plastic leaded chip carrier (plcc) industrial ia80c152jb/jd - plc68i - r - 01 (rohs - compliant package) n8 0c152jb n80c152jb1 n80c152jd n80c152jd1 ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 58 of 61 1 - 888 - 824 - 4184 9. errata the following errata are associated with all version s of the ia80c152 . a workaround to the identified problem has been provided where possible. 9.1 errata summary table 36 presents a summary of errata. table 36 . summary of errata errata no. problem rev. 01 1 under certain circumstances, the dma arbiter will D lock up in alternate cycles mode. this problem occurs when one dma channel has finished performing a transfer and another dma initiates a transfer with the byte count register having been set to 0001 by the cpu. exists 2 original intel device has a linear resistor as the pullup on input reset. exists 3 dma can interfere with processing of interrupts of different priority. exis ts 4 corruption of read data may occur if port 0 bit written to 0 . exists 9.2 errata detail errata no. 1 problem: under certain circumstances, the dma arbiter will D lock up in alternate cycles mode. this problem occurs when one d ma channel has finished performing a transfer and another dma initiates a transfer with the byte count register having been set to 0001 by the cpu. workaround: avoid using the alternate cycles dma mode in conjunction with a byte count of one. errata no. 2 problem: original intel device has a linear resistor as the pullup on input reset. workaround: none. a non - linear resistor is on the innovasic device. this may affect operation of certain r/c reset circuits. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 59 of 61 1 - 888 - 824 - 4184 errata no. 3 problem: dma can interfere with processing of interrupts of different priority . description: the following sequence of events must occur for th is issue to occur : 1. a low - priority (associated priority bit not set) interrupt is accepted by the processor, but vector fetch is delayed by a dma cycle. 2. during dma cycle, a high - priority (associated priority bit set) interrupt is accepted. 3. after dma cycle, the high - priority vector is fetched. no further processing of any low - priority interrupts will occur. workaround: use inherent prioritization of interrupts (all interrupts set to high or low priority only) if dma is enabled. errata no. 4 problem: corruption of read data may occur if port 0 bit written to 0 . description: if any bit in port 0 is written to a 0 while the device is configured to use p0 as address/data bus, corruption of read data may occur. workaround: write all port 0 register bits to a 1 while using p0 as address/data bus. ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 60 of 61 1 - 888 - 824 - 4184 revision history table 37 presents the sequence of revisions to document ia 211 040524 . table 37 . revision history date revision description page(s) august 17 , 200 5 1 e dition released. na july 27, 2007 2 renamed data sheet for clarity na august 31, 2007 3 updated errata and roh s information 57, 58 june 18, 2009 4 document reformatted to meet publication standards . added conventions , acronyms and abbreviations , and summary of errata table . added new errata and added range for supply voltage in table 9 . all august 17, 2009 5 added a note regarding recommendations for using the jb/jd version of the device in ja/jc applications. revised tables 2, 3 and 5. 7, 11, 12, 15 july 29, 2010 6 errata 3 and 4 added. 58, 59 ?
ia 80c152 data sheet universal communications controller july 29 , 2010 ia21104 0 524 - 06 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 61 of 61 1 - 888 - 824 - 4184 10. for additional information the ia80c152 is a Dplug - and - play drop - in replacement for the original intel 80c152 . innovasic produces replacement ics using its miles, or managed ic lifetime extension syst em, cloning technology. this technology produces replacement ics far more complex than Demulation while ensuring they are compatible with the original ic. miles captures the design of a clone so it can be produced even as silicon technology advances. m iles also verifies the clone against the original ic so that even the Dundocumented features are duplicated. this data sheet presents engineering information about the ia80c152 including functional and i/o descriptions, electrical characteristics, and ap plicable timing. the innovasic support team wants its information to be complete, accurate, useful, and easy to understand. please feel free to contact experts at innovasic with suggestions, comments, or questions at any time . innovasic support team 3737 princeton ne suite 130 albuquerque, nm 87107 (505) 883 - 5263 fax: (505) 883 - 5477 toll free: (888) 824 - 4184 e - mail: support@innovasic.com website: http://www.innovas ic.com ?

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